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1 isl80102, isl80103 high performance 2a and 3a linear regulators isl80102, isl80103 the isl80102 and isl80103 are low voltage, high-current, single output ldos specified for 2a and 3a output current, respectively. these ldos operate from input voltages of 2.2v to 6v and are capable of providing output voltages of 0.8v to 5v on the adjustable v out versions. fixed output voltage options are available in 1.5v, 1.8v, 2.5v, 3.3v and 5v. other custom voltage options available upon request. for applications that demand in-rush current less than the current limit, an external capacitor on the soft start pin provides adjustment. the enable feature allows the part to be placed into a low quiescent current shutdown mode. a sub-micron bicmos pr ocess is utilized for this product family to deliver the best in class analog performance and overall value. these cmos ldos will consume significantly lower quiescent current as a function of load over bipolar ldos, which translates into higher efficiency and the ability to consider packages with smaller footprints. quiescent current is modestly compromised to enable a leading class fast load transient response, and hence a lower total ac regulation band for an ldo in this category. features ? stable with all capacitor types (note 11) ? 2a and 3a output current ratings ? 2.2v to 6v input voltage range ?1.8% v out accuracy guaranteed over line, load and t j = -40c to +125c ? very low 120mv dropout voltage at 3a (isl80103) ? fixed and adjustable v out versions ? very fast transient response ? excellent 62db psrr ?100v rms output noise ? power-good output ? adjustable in-rush current limiting ? short circuit and over-temperature protection ? available in a 10 ld dfn (now), 5ld to220 and 5ld to263 (soon) applications* (see page 14) ?servers ? telecommunications and networking ?medical equipment ? instrumentation systems ?routers and switchers typical application isl80102, isl80103 vin 9 vin 10 enable 7 ss 6 gnd 2.5v 10% c in 10f v in off on *c ss 5 pg 4 vout 1 vout 2 v out 1.8v 1.8% c out 10f r pg 100k sense 3 pgood *css is optional, (see note 12) on page 5. caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2009, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. march 22, 2010 fn6660.1
isl80102, isl80103 2 fn6660.1 march 22, 2010 block diagram 10a 10a r7 r8 r9 r5 m5 m4 en en en en en enable m7 500mv 485mv 500mv m3 power pmos m1 vin vout sense r1 r4 r2 *r3 gnd pg adj level shift m2 + - + - + - + - + - + - + - v to i ss il/10,000 il m6 m8 en *r3 is open for adj versions. ordering information part number (notes 1, 2, 4) part marking v out voltage temp. range (c) package (pb-free) pkg dwg. # isl80102irajz dzja adj -40 to +125 10 ld 3x3 dfn l10.3x3 isl80102ir15z dzma 1.5v (note 3) -40 to +125 10 ld 3x3 dfn l10.3x3 isl80102ir18z dzna 1.8v -40 to +125 10 ld 3x3 dfn l10.3x3 isl80102ir25z dzpa 2.5v -40 to +125 10 ld 3x3 dfn l10.3x3 isl80102ir33z dzra 3.3v (note 3) -40 to +125 10 ld 3x3 dfn l10.3x3 isl80102ir50z dzsa 5.0v (note 3) -40 to +125 10 ld 3x3 dfn l10.3x3 isl80103irajz dzaa adj -40 to +125 10 ld 3x3 dfn l10.3x3 isl80103ir15z dzda 1.5v (note 3) -40 to +125 10 ld 3x3 dfn l10.3x3 isl80103ir18z dzea 1.8v -40 to +125 10 ld 3x3 dfn l10.3x3 isl80103ir25z dzfa 2.5v -40 to +125 10 ld 3x3 dfn l10.3x3 isl80103ir33z dzga 3.3v (note 3) -40 to +125 10 ld 3x3 dfn l10.3x3 isl80103ir50z dzha 5.0v (note 3) -40 to +125 10 ld 3x3 dfn l10.3x3 notes: 1. add ?-t? or ?-tk? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). inte rsil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. the 1.5v, 3.3v and 5v fixed output voltages will be released in the future. please contact in tersil marketing for more detail s. 4. for moisture sensitivity level (msl), please see device in formation page for isl80102 , isl80103 . for more information on msl please see tech brief tb363 . isl80102, isl80103
isl80102, isl80103 3 fn6660.1 march 22, 2010 pin configuration isl80102, isl80103 (10 ld 3x3 dfn) top view 2 3 4 1 5 9 8 7 10 6 v out v out sense/adj pg gnd v in v in dnc enable ss pin descriptions pin number pin name description 1, 2 v out output voltage pin. 3sense/adjremote voltage se nse for internally fixed v out options. adj pin for externally set v out . 4pgv out in regulation signal. logic low defines when v out is not in regulation. must be grounded if not used. 5gndgnd pin. 6 ss external cap adjusts in-rush current. 7enable v in independent chip enable. ttl and cmos compatible. 8 dnc do not connect this pin to ground or supply. leave floating. 9, 10 v in input supply pin. epad epad at ground potential. soldering it directly to gnd plane is optional. typical application figure 1. typical application diagram isl80102, isl80103 vin 9 vin 10 enable 7 ss 6 gnd 2.5v 10% c in 10f v in *c ss 5 pg 4 vout 1 vout 2 v out 1.8v c out 10f r pg 100k adj 3 pgood r 1 10k r 4 1.0k **c pb 1500pf en open drain compatible *css is optional, (see note 12) on page 5. **c pb is optional. see ?functional description? on page 12 for more information. r 3 2.61k isl80102, isl80103
isl80102, isl80103 4 fn6660.1 march 22, 2010 absolute maximum ratings (note 7) thermal information v in relative to gnd . . . . . . . . . . . . . . . . . . -0.3v to +6.5v v out relative to gnd . . . . . . . . . . . . . . . . . -0.3v to +6.5v pg, enable, sense/adj, ss relative to gnd. . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v recommended operating conditions (note 10) junction temperature range (t j ) . . . . . . . -40c to +125c vin relative to gnd . . . . . . . . . . . . . . . . . . . . . 2.2v to 6v v out range . . . . . . . . . . . . . . . . . . . . . . . . . . 800mv to 5v pg, enable, sense/adj, ss relative to gnd . . . . . 0v to 6v pg sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma thermal resistance (typical) ja (c/w) jc (c/w) 10 ld 3x3 dfn package (notes 5, 6) 48 4 maximum junction temperature (plastic package). . . +150c storage temperature range . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 7. abs max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6v of 1%. electrical specifications unless otherwise noted, all parameters ar e established over the following specified conditions: v in = v out + 0.4v, v out = 1.8v, c in = c out = 10f, t j = +25c, i load = 0a applications must follow thermal guidelines of the package to determine worst case junction temperature. please refer to ?functional description? on page 12 and tech brief tb379 . boldface limits apply over the operatin g temperature range, -40c to +125c. pulse load techniques used by ate to ensure t j = t a defines establ ished limits. parameter symbol test conditions min (note 8) typ max (note 8) units dc characteristics dc output voltage accuracy v out v out options: 1.8v. v in =2.2v; i load = 0a 0.5 % v out options: 1.8v. 2.2v < v in < 3.6v; 0a < i load < 3a -1.8 1.8 % v out options: 2.5v v in =v out + 0.4v; i load = 0a 0.5 % v out options: 2.5v v out + 0.4v < v in < 6v; 0a < i load < 3a -1.8 -1.8 % feedback pin (adj version) v fb 2.2v < v in < 6v, 0a < i load < 3a 491 500 509 mv dc input line regulation v out / v in v out + 0.4v < v in < 3.6v, v out = 1.8v 0.1 0.4 % v out + 0.4v < v in < 6v, v out = 2.5v 0.1 0.8 % dc output load regulation v out / i out 0a < i load < 3a, all voltage options -0.8 % 0a < i load < 2a, all voltage options -0.6 % feedback input current v adj = 0.5v 0.01 1 a ground pin current i q i load = 0a, 2.2v < v in < 6v 7.5 9 ma i load = 3a, 2.2v < v in < 6v 8.5 12 ma ground pin current in shutdown i shdn enable pin = 0.2v, v in = 5v 0.4 a enable pin = 0.2v, v in = 6v 3.3 16 a dropout voltage (note 9) v do i load = 3a, v out = 2.5v, 10 ld 3x3 dfn 120 185 mv i load = 2a, v out = 2.5v, 10 ld 3x3 dfn 81 125 mv isl80102, isl80103
isl80102, isl80103 5 fn6660.1 march 22, 2010 output short circuit current (3a version) isc v out = 0v, v out + 0.4v < v in < 6v 5.0 a output short circuit current (2a version) v out = 0v, v out + 0.4v < v in < 6v 2.8 a thermal shutdown te m p e ra t u r e tsd v out + 0.4v < v in < 6v 160 c thermal shutdown hysteresis (rising threshold) tsdn v out + 0.4v < v in < 6v 15 c ac characteristics input supply ripple rejection psrr f = 1khz, i load = 1a; v in = 2.2v 55 db f = 120hz, i load = 1a; v in = 2.2v 62 output noise voltage i load = 10ma, bw = 300hz < f < 300khz 100 v rms enable pin characteristics turn-on threshold v en(high) 2.2v < v in < 6v 0.3 0.8 0.95 v hysteresis (rising threshold) v en(hys) 2.2v < v in < 6v 135 mv enable pin turn-on delay t en c out = 10f, i load = 1a 150 s enable pin leakage current v in = 6v, en = 3v 1 a soft-start characteristics reset pull-down resistance r pd 323 soft start charge current i chg -7 -4.5 -2 a pg pin characteristics v out pg flag threshold 75 84 92 %v out v out pg flag hysteresis 4% pg flag low voltage i sink = 500a 47 100 mv pg flag leakage current v in = 6v, pg = 6v 0.05 1 a notes: 8. parameters with min and/or max limits are 100% tested at +2 5c, unless otherwise specified. temperature limits established by characterization and ar e not production tested. 9. dropout is defined by the difference in supply v in and v out when the supply produces a 2% drop in v out from its nominal value. 10. electromigration specification defined as lifetime average junction temperature of +110c where max rated dc current = lifetime average current. 11. minimum cap of 10f x5r/x7r on v in and v out required for stability. 12. if the current limit for in-rush current is acceptable in application, do not use this feature. used only when large bulk ca pacitance required on v out for application. electrical specifications unless otherwise noted, all parameters ar e established over the following specified conditions: v in = v out + 0.4v, v out = 1.8v, c in = c out = 10f, t j = +25c, i load = 0a applications must follow thermal guidelines of the package to determine worst case junction temperature. please refer to ?functional description? on page 12 and tech brief tb379 . boldface limits apply over the operatin g temperature range, -40c to +125c. pulse load techniques used by ate to ensure t j = t a defines establ ished limits. parameter symbol test conditions min (note 8) typ max (note 8) units isl80102, isl80103
isl80102, isl80103 6 fn6660.1 march 22, 2010 typical operating performance unless otherwise noted: v in = 2.2v, v out = 1.8v, c in = c out = 10f, t j = +25c, i l = 0a. figure 2. v out vs temperature figure 3. output voltage vs supply voltage figure 4. v out vs output current figure 5. ground current vs supply voltage figure 6. ground current vs output current figure 7. ground current vs output voltage 1.8 1.2 0.6 0 -0.6 -1.2 -1.8 -50 -25 0 25 50 75 100 125 150 v out (%) junction temperature (c) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0246 supply voltage (v) output voltage (v) 135 +125c +25c -40c -1.8 -1.2 -0.6 0.0 0.6 1.2 1.8 0 0.5 1.0 1.5 2.0 2.5 3.0 output current (a) v out (%) +125c +25c -40c 0 1 2 3 4 5 6 7 8 9 2 input voltage (v) ground current (ma) 3456 7.5 7.7 7.9 8.1 8.3 8.5 8.7 8.9 9.1 0 0.5 1.0 1.5 2.0 2.5 3.0 output current (a) ground current (ma) +125c +25c -40c 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 0.8 1.4 2.0 2.6 3.2 3.8 4.4 5.0 output voltage (v) current (ma) +125c +25c -40c isl80102, isl80103
isl80102, isl80103 7 fn6660.1 march 22, 2010 figure 8. shutdown current vs temperature figure 9. shutdown current vs temperature figure 10. dropout voltage vs temperature figure 11. dropout voltage vs output current figure 12. enable threshold voltage vs temperature figure 13. power-up (v in = 2.2v) typical operating performance unless otherwise noted: v in = 2.2v, v out = 1.8v, c in = c out = 10f, t j = +25c, i l = 0a. (continued) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) ground current (a) v in = 5v 0 1 2 3 4 5 6 7 8 9 10 11 12 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) ground current (a) v in = 6v 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) dropout voltage (mv) 1a 2a 3a 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 0 0.5 1.0 1.5 2.0 2.5 3.0 output current (a) dropout voltage (mv) 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) voltage (v) v in (1v/div) ss (1v/div) v out (1v/div) time (10ms/div) pg (1v/div) isl80102, isl80103
isl80102, isl80103 8 fn6660.1 march 22, 2010 figure 14. power-down (v in = 2.2v) figure 15. enable start-up figure 16. enable shutdown figure 17. start-up time vs supply voltage figure 18. start-up time vs temperature figure 19. current limit vs temperature typical operating performance unless otherwise noted: v in = 2.2v, v out = 1.8v, c in = c out = 10f, t j = +25c, i l = 0a. (continued) v in (1v/div) ss (1v/div) v out (1v/div) time (10ms/div) pg (1v/div) ss (1v/div) v out (1v/div) pg (1v/div) time (50s/div) en (1v/div) ss (1v/div) v out (1v/div) pg (1v/div) time (5ms/div) en (1v/div) 0 50 100 150 200 250 300 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input voltage (v) start-up time (s) 0 50 100 150 200 250 300 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) start-up time (s) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) current limit (a) isl80102 isl80103 isl80102, isl80103
isl80102, isl80103 9 fn6660.1 march 22, 2010 figure 20. current limit vs supply voltage figure 21. current limit response (isl80102) figure 22. thermal cycling (isl80102) figure 23. current limit response (isl80103) figure 24. thermal cycling (isl80103) figure 25. in-rush current with no soft-start capacitor, c out = 1000f typical operating performance unless otherwise noted: v in = 2.2v, v out = 1.8v, c in = c out = 10f, t j = +25c, i l = 0a. (continued) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input voltage (v) current limit (a) isl80102 isl80103 i out (1a/div) v out (1v/div) time (10ms/div) i out (1a/div) v out (1v/div) time (100ms/div) i out (2a/div) v out (1v/div) time (20ms/div) i out (2a/div) v out (1v/div) time (50ms/div) i out (2a/div) v out (1v/div) time (1ms/div) en (1v/div) isl80102, isl80103
isl80102, isl80103 10 fn6660.1 march 22, 2010 figure 26. in-rush with 22nf soft-start capacitor, c out = 1000f figure 27. in-rush with 47nf soft-start capacitor, c out = 1000f figure 28. load transient 0a to 3a, c out =10f ceramic figure 29. load transient 0a to 3a, c out = 10f ceramic + 100f oscon figure 30. load transient 1a to 3a, c out =10f ceramic figure 31. load transient 1a to 3a, c out = 10f ceramic + 100f oscon typical operating performance unless otherwise noted: v in = 2.2v, v out = 1.8v, c in = c out = 10f, t j = +25c, i l = 0a. (continued) i out (2a/div) v out (1v/div) time (1ms/div) en (1v/div) i out (2a/div) v out (1v/div) time (1ms/div) en (1v/div) di/dt = 30a/s time (200s/div) v out (50mv/div) i out (2a/div) di/dt = 30a/s time (200s/div) v out (50mv/div) i out (2a/div) di/dt = 30a/s time (200s/div) v out (50mv/div) i out (2a/div) di/dt = 30a/s time (200s/div) v out (50mv/div) i out (2a/div) isl80102, isl80103
isl80102, isl80103 11 fn6660.1 march 22, 2010 figure 32. load transient 0a to 3a, c out = 10f ceramic, no c pb (adj version) figure 33. load transient 0a to 3a, c out = 10f ceramic, c pb = 1500pf (adj version) figure 34. line transient figure 35. psrr vs load figure 36. psrr vs c out figure 37. spectral noise density vs frequency typical operating performance unless otherwise noted: v in = 2.2v, v out = 1.8v, c in = c out = 10f, t j = +25c, i l = 0a. (continued) di/dt = 3a/s time (50s/div) v out (20mv/div) i out (2a/div) di/dt = 3a/ sec di/dt = 3a/s time (50s/div) v out (20mv/div) i out (2a/div) v out (10mv/div) v in (1v/div) time (200s/div) 3.2v 2.2v 0 10 20 30 40 50 60 70 80 db 10 100 1k 10k 100k 1m frequency (hz) 1a 100ma 10 100 1k 10k 100k 1m frequency (hz) 0 10 20 30 40 50 60 70 80 db i l = 100ma 10f 100f 47f 0.01 0.1 1 10 10 100 1k 10k 100k 1m frequency (hz) noise v/ hz isl80102, isl80103
isl80102, isl80103 12 fn6660.1 march 22, 2010 functional description input voltage requirements despite other output voltages offered, this family of ldos is optimized for a true 2.5v to 1.8v conversion where the input supply can have a tolerance of as much as 10% for conditions noted in the ?electrical specifications? table on page 4. minimum guaranteed input voltage is 2.2v, however, due to the nature of an ldo, v in must be some margin higher than the output voltage plus dropout at the maximum rated current of the application if active filtering (psrr) is expected from v in to v out . the dropout spec of this family of ldos has been generously specified in order to allow applications to design for a level of efficiency that can accommodate the smaller outline package for those applications that cannot accommodate the profile of the to220/263. enable operation the enable turn-on threshold is typically 770mv with a hysteresis of 135mv. an internal pull-up or pull-down resistor is available upon request. as a result, this pin must not be left floating. this pin must be tied to v in if it is not used. a 1k to 10k pull-up resistor will be required for applications that use open collector or open drain outputs to control the enable pin. the enable pin may be connected directly to v in for applications that are always on. power-good operation applications not using this feature must connect this pin to ground. the pgood flag is an open-drain nmos that can sink up to 10ma during a fault condition. the pgood pin requires an external pull-up resistor which is typically connected to the vout pin. the pgood pin should not be pulled up to a voltage source greater than v in . the pgood fault can be caused by the output voltage going below 84% of the nominal output voltage, or the current limit fault, or low input voltage. the pgood does not function during thermal shutdown. the pgood functions in shutdown. soft-start operation (optional) if the current limit for in-rush current is acceptable in the application, do not use this feature. the soft-start circuit controls the rate at which the output voltage comes up to regulation at power-up or ldo enable. a constant current charges an external soft-start capacitor. the external capacitor always gets discharged to ground pin potential at the beginning of start-up or enabling. the discharge rate is the rc time constant of r pd and c ss . see figures 25 through 28 in the ?typical operating performance curves? beginning on page 10. r pd is the on-resistance of the pull down mosfet, m8. r pd is 300 typically. the soft-start feature effectively reduces the in-rush current at power-up or ldo enable until v out reaches regulation. the in-rush current can be an issue for applications that require large, external bulk capacitances on v out where high levels of charging current can be seen for a significant period of time. the in-rush currents can cause v in to drop below minimum which could cause v out to shutdown. figure 38 shows the relationship between in-rush current and c ss with a c out of 1000f. output voltage selection an external resistor divider is used to scale the output voltage relative to the internal reference voltage. this voltage is then fed back to th e error amplifier. the output voltage can be programmed to any level between 0.8v and 5v. an external resistor divider, r 3 and r 4 , is used to set the output voltage as shown in equation 1. the recommended value for r 4 is 500 to 1k . r 3 is then chosen according to equation 2: external capacitor requirements external capacitors are requ ired for proper operation. careful attention must be paid to the layout guidelines and selection of capacitor type and value to ensure optimal performance. output capacitor the isl80102, isl80103 applies state-of-the-art internal compensation to keep selection of the output capacitor simple for the customer. stable operation over full temperature, v in range, v out range and load extremes are guaranteed for all capacitor types and values assuming a 10f x5r/x7r is used for local bypass on v out . this minimum capacitor must be connected to v out and ground pins of the ldo with pcb traces no longer than 0.5cm. lower cost y5v and z5u type ceramic capacitors are acceptable if the size of the capacitor is larger to compensate for the significantly lower tolerance over x5r/x7r types. additional capacitors of any value in ceramic, poscap or alum/tantalum electrolytic types may be placed in parallel to improve psrr at higher 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 20406080100 c ss (nf) in-rush current limit (a) figure 38. in-rush current vs soft-start capacitance v out 0.5v r 3 r 4 ------ - 1 + ?? ?? ?? = (eq. 1) r 3 r 4 v out 0.5v --------------- - 1 ? ?? ?? = (eq. 2) isl80102, isl80103
isl80102, isl80103 13 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6660.1 march 22, 2010 for additional products, see www.intersil.com/product_tree frequencies and/or load tr ansient ac output voltage tolerances. input capacitor the minimum input capacitor required for proper operation is 10f having a ceramic dielectric. this minimum capacitor must be connected to v in and ground pins of the ldo with pcb traces no longer than 0.5cm. phase boost capacitor (optional) the isl80102 and isl80103 are designed to be stable with 10f or larger ceramic capacitor. applications using the adj versions, may see improved performance with the addition of a small ceramic capacitor c pb as shown in figure 1 on page 3. the conditions where c pb may be beneficial are: (1) v out > 1.5v, (2) c out = 10f, and (3) tight ac voltage regulation band. c pb introduces phase lead with the product of r 3 and c pb that results in increasing the bandwidth of the ldo. ty pi c a l r 3 x c pb should be 4 s. c pb not recommended for v out < 1.5v. current limit protection the isl80102, isl80103 family of ldos incorporates protection against overcurrent due to short, overload condition applied to the output and the in-rush current that occurs at start-up. the ldo performs as a constant current source when the output current exceeds the current limit threshold noted in the ?electrical specifications? table on page 4. if the short or overload condition is removed from v out , then the output returns to normal voltage mode regulation. in the event of an overload condition, the ldo might begin to cycle on and off due to the die temperature exceeding the thermal fault condition. the to220/263 package will tolerate higher levels of power dissipation on the die which may never thermal cycle if the heatsink of this larger package can keep the die temperature below the specified typical thermal shutdown temperature. power dissipation and thermals the junction temperature must not exceed the range specified in the ?recommended operating conditions (note 10)? on page 4. the power dissipation can be calculated by using equation 3: the maximum allowable junction temperature, t j(max) and the maximum expected ambient temperature, t a(max) will determine the maximum allowable power dissipation as shown in equation 4: where ja is the junction-to-ambient thermal resistance. for safe operation, please make sure that power dissipation calculated in equation 3, p d be less than the maximum allowable power dissipation p d(max) . the dfn package uses the copper area on the pcb as a heat-sink. the epad of this package must be soldered to the copper plane (gnd plane) for heat sinking. figure 39 shows a curve for the ja of the dfn package for different copper area sizes. thermal fault protection in the event the die temperature exceeds typically +160c, then the output of the ldo will shut down until the die temperature can cool down to typically +145c. the level of power combined with the thermal impedance of the package (+48c/w for dfn) will determine if the junction temperature exceeds the thermal shutdown temperature. p d v in v out ? () i out v in i gnd + = (eq. 3) p dmax () t jmax () t a ? () ja ? = (eq. 4) figure 39. 3mmx3mm-10 pin dfn on 4-layer pcb with thermal vias ja vs epad-mount copper land area on pcb 46 44 42 40 38 36 34 ja , c/w 2 4 6 8 10 12 14 16 18 20 22 24 epad-mount copper land area on pcb, mm 2 isl80102, isl80103
isl80102, isl80103 14 fn6660.1 march 22, 2010 products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: isl80102 , isl80103 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 3/4/10 fn6660.1 corrected features on page 1 as follows: -changed bullet "? 185mv dropout @ 3a, 125mv dropout @ 2a" to "? very low 120mv dropout at 3a" -changed bullet "? 65db typica l psrr" to "? 62db typical psrr" -deleted 0.5% initial vout accuracy modified figure 1 and placed as typical application on page 1. moved pinout to page 3 in "block diagram" on page 2, corrected resistor associated with m5 from r4 to r5 updated block diagram on page 2 as follows? - added m8 from ss to ground. updated figure 1 on page 3 as follows: -corrected pin 6 from ss to irset -removed note 12 callout "minimum cap on vin and vout required for stability." added note "*css is optional. see note 12 on page 5. " and ?** cpb is optional. see ?functional description? on page 12 for more information.? added "the 1.5v, 3.3v and 5v fixed output voltages will be released in the future." to note 3 on page 2. in ?thermal information? on page 4, updated theta ja from 45 to 48 per asyd in ?soft-start operation (optional)? on page 12: -changed "the external capacitor always gets disc harged to 0v at start-up of after coming out of a chip disable." to "the exte rnal capacitor always gets discharged to ground pin potential at start-up or enabling." -changed "the soft-start function effectively limits the amount of in-rush current below the programmed current limit during start-up or an enable sequence to avoid an overcurrent fault condition." to "the soft-start feature effectiv ely reduces the in-rush current at power-up or ldo enable until vout reaches regulation." -added "see figures 25 through 27 in the ?typ ical operating performance curves? beginning on page 9." -added ?rpd is the on resistance of the pull down mosfet, m8. rpd is 300ohms typically.? added "phase boost capacitor (cpb)" section on page 13. in ?typical operating performance? on page 11, revised figure "psrr vs vin" which had 3 curves with "spectral noise density vs frequency" which has one curve. added "figure 32. load transient 0a to 3a, cout = 10f ceramic, no cpb (adj version)" and "figure 33. load transient 1a to 3a, cout = 10f ceramic, cpb = 1500pf (adj version)" 09/30/09 fn6660.0 initial release. isl80102, isl80103
isl80102, isl80103 15 fn6660.1 march 22, 2010 isl80102, isl80103 package outline drawing l10.3x3 10 lead dual flat package (dfn) rev 6, 09/09 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.18mm and 0.30mm from the terminal tip. lead width applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.10 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail "x" c c 5 6 6 a b 0.10 c 1 package 1.00 0.20 8x 0.50 2.00 3.00 (10x 0.23) (8x 0.50) 2.00 1.60 (10 x 0.55) 3.00 0.05 0.20 ref 10 x 0.23 10x 0.35 1.60 outline max (4x) 0.10 ab 4 c m 0.415 0.23 0.35 0.200 2 4

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